\doxysubsubsubsection{RCC MCOx Clock Prescaler }
\hypertarget{group___r_c_c___m_c_ox___clock___prescaler}{}\label{group___r_c_c___m_c_ox___clock___prescaler}\index{RCC MCOx Clock Prescaler@{RCC MCOx Clock Prescaler}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga438d8c3bead4e1ec5dd5757cb0313d53}\label{group___r_c_c___m_c_ox___clock___prescaler_ga438d8c3bead4e1ec5dd5757cb0313d53} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+1}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}}
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\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga6198330847077f4da351915518140bfc}\label{group___r_c_c___m_c_ox___clock___prescaler_ga6198330847077f4da351915518140bfc} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+2}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}}
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\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_gab9dac03733c3c5bd8877ef43bff3d5f4}\label{group___r_c_c___m_c_ox___clock___prescaler_gab9dac03733c3c5bd8877ef43bff3d5f4} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+3}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}})
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\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga1bdc2eb56aaeb53dc3ca5cd72f22d4c8}\label{group___r_c_c___m_c_ox___clock___prescaler_ga1bdc2eb56aaeb53dc3ca5cd72f22d4c8} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+4}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}}
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\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga67292dd05ceb8189ec439d4ac4d58b88}\label{group___r_c_c___m_c_ox___clock___prescaler_ga67292dd05ceb8189ec439d4ac4d58b88} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+5}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}})
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\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga0229b0d7e7444342b5966d4096d61b1b}\label{group___r_c_c___m_c_ox___clock___prescaler_ga0229b0d7e7444342b5966d4096d61b1b} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+6}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}})
\item 
\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_gad32c07babb81067c9243e81cc02d6f5d}\label{group___r_c_c___m_c_ox___clock___prescaler_gad32c07babb81067c9243e81cc02d6f5d} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+7}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}})
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\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_gadb84d9a10db2c49376be8fada619fe08}\label{group___r_c_c___m_c_ox___clock___prescaler_gadb84d9a10db2c49376be8fada619fe08} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+8}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}}
\item 
\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga0e12a28a4762fd6d7826a8349b44f0f6}\label{group___r_c_c___m_c_ox___clock___prescaler_ga0e12a28a4762fd6d7826a8349b44f0f6} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+9}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga160aca969815d45c15c0aaa3e84f7a53}\label{group___r_c_c___m_c_ox___clock___prescaler_ga160aca969815d45c15c0aaa3e84f7a53} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+10}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga18c9fea34a100746a2ad7fc117bc2036}\label{group___r_c_c___m_c_ox___clock___prescaler_ga18c9fea34a100746a2ad7fc117bc2036} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+11}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga0e15b47a23cc0f7b31a737736d64bb3f}\label{group___r_c_c___m_c_ox___clock___prescaler_ga0e15b47a23cc0f7b31a737736d64bb3f} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+12}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga7b99a9858094aa608be6bfefed3b701e}\label{group___r_c_c___m_c_ox___clock___prescaler_ga7b99a9858094aa608be6bfefed3b701e} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+13}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8007a9d6ee3fd88912aaf290746ae0e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+0}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_ga539f249e2ac961eb38327b74fceea5d7}\label{group___r_c_c___m_c_ox___clock___prescaler_ga539f249e2ac961eb38327b74fceea5d7} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+14}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf7c1280f61d56b4897f9c876987e092}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11e1d10d1b55e0d88d24212ea2c8ba6e}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad8ebcaff127fd7a89e83e450cca28e4d}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE\+\_\+3}})
\item 
\Hypertarget{group___r_c_c___m_c_ox___clock___prescaler_gaecc7121d3dffe60e59e490c809dd8ad0}\label{group___r_c_c___m_c_ox___clock___prescaler_gaecc7121d3dffe60e59e490c809dd8ad0} 
\#define {\bfseries RCC\+\_\+\+MCODIV\+\_\+15}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga23171ca70972a106109a6e0804385ec5}{RCC\+\_\+\+CFGR\+\_\+\+MCO1\+PRE}}
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
